INTEL HOUSE

So, let's examine each of the above items in more detail. First, the new computational core is based on the highly efficient and well-proven Core architecture. Indeed, Core 2 Duo and Core 2 Quad demonstrate a superb combination of high performance, balanced heat emission, and the optimum price. But the Core architecture has some fundamental problems which are not seen to the regular user. The most important of them is the difficulty of scaling or, in simpler terms, in the problems that arise as the number of cores goes up within a single processor. Originally, the Core architecture was developed for use in a two-core make. But once the need for 4-core processors arose, the only possible solution was to merge two dual-core chips within a single package. That resulted in a problem related to the interaction of cores with one another. The thing is, the Quad Pumped Bus has long exhausted its capability and does not allow data exchange among the cores directly. At the same time, its bandwidth did not meet the requirements in multi-core systems. And the more cores, the more vivid the shortcomings of the QPB were. Clearly, Intel could not stand up with that situation and shaped the course towards the increase in the number of cores. That resulted in the birth of the new QPI (Quick Path Interconnects) bus with the "point-to-point" topology. Data is transmitted over two 20-bit wide connections, with 16 bits allocated for data transmission. The resultant bandwidth is 25.6 GB/s, which is approximately equal to that of the HyperTransport v3.0 bus.The second important change in the architecture of the processor applies to the structure and the size of the cache memory. As compared to the Penryn core, the L1 cache size in Nehalem has not changed. Its size is 64 K, of which 32 K is allocated for data, and 32 K - for instructions. As regards the L2 cache memory size, the changes are more substantial - instead of a large shared cache, the engineers at Intel have equipped each core with its own L2 cache of 256 K in size. Also, Nehalem has acquired the shared L3 cache memory of 8 MB in size (for the Bloomfield core).
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